1. Field of the Invention
The invention relates to analog-digital converters, namely electronic circuits that can be used to convert an analog input signal into a precise digital value representing the amplitude of the analog signal. The digital value is obtained in the form of a word of several bits, generally encoded in pure binary mode.
Several conversion methods exist and the choice of one method rather than another depends on the performance characteristics expected of the converter. The most important parameters of these performance characteristics are:
the resolution defined by the number of bits of the output mode representing the amplitude of the analog signal with exactness; the number of bits may from 16 to 18, or even 20, for the most precise converters, and the precision is generally within plus or minus 1/2 the least significant bit.; PA1 the speed, namely the number of conversion operations that can be done in one second; PA1 the power consumption: a fast and precise converter consumes far more energy than a slow, low-precision converter; now the consumption of power leads to a heating of the integrated circuit chip on which the converter is made. This heating should be compensated for by cooling means that make it hard to use the circuit when there are space requirement constraints to be met; PA1 and of course the cost of designing and manufacturing the converter, related especially to the integrated circuit chip surface used by the converter. PA1 successive approximation converters that compare the input analog signal Vin successively with digital values that, at each time, approach the value of the analog signal more closely; these converters work in at least N phases if the value is encoded on N bits. They are generally very slow for values of precision exceeding 6 or 8 bits. PA1 flash converters which use 2.sup.N comparators in parallel; the comparators each receive, firstly, the analog signal and, secondly, one of 2.sup.N reference voltages defined by a bridge of 2.sup.N precision resistors; these converters are very fast (generally two phases) but they are very bulky and consume a great deal of power when N reaches 10 to 12 bits; PA1 combined converters which have a coarse converter to obtain most significant bits and a fine converter to obtain least significant bits; the coarse converter may be a high-speed and low-precision converter (with a precision of 4 to 6 bits for example); the fine converter must be precise even when it is less speedy.
The qualities of an analog-digital converter result from a compromise among the above parameters and an aim of the present invention is to obtain a better compromise of this kind.
2. Description of the Prior Art
The known structures of analog-digital converters include:
Among the combined converters, several approaches have already been proposed.
In one approach, the coarse converter is a flash converter that gives P bits which are the most significant bits. This value is reconverted into an analog signal by a P bit digital-analog converter. The difference between the analog signal Vin and this reconverted value, also called a remainder or residue, is converted by a fine converter which determines the least significant bits of the conversion. There is a gain in power consumption and space requirement as compared with a flash converter, but the digital-analog conversion takes time and calls for a precise servocontrol of the gains of the different circuit parts (the analog-digital and digital-analog converters).
Another architecture of a combined converter uses what is known as an input analog signal folding converter. The input signal Vin is applied to at least two folding circuits with the function of giving signals called "folded" signals Vr1, Vr1b, Vr2, Vr2b having an amplitude that varies with the amplitude of the input signal Vin according to a periodic function (having an approximately sinusoidal shape). The differences (Vr1-Vr1b), (Vr2-Vr2b) between the folded signals coming from two blocks get nullified periodically for input voltage values that are reference voltages defined by a bridge of resistors. On the basis of these differences, signals called "interpolated" signals are set up. These interpolated signals have the same general form as the differences of folded signals, but get nullified for the intermediate input voltage values between the reference values.
The interpolated signals can then be used to obtain the least significant bits of the digital-analog conversion, representing the position of Vin with respect to these intermediate reference values. The most significant bits are given by a coarse converter that indicates the "period" of the folded signals in which the analog input voltage Vin is located, i.e. it indicates the adjacent values of reference voltages in between which Vin is located.
In a previously proposed architecture, the interpolation circuit comprises simple bridges of resistors that receive, for example, the differences (Vr1-Vr2) and (Vr1b-Vr2b) between the folded signals. The intermediate connections of these bridges of resistors give the interpolated signals; they are applied two by two to comparators that switch over in one direction or the other according to the value of the interpolated signals, hence according to the position of Vin between two adjacent reference voltages.
In another architecture, the interpolation circuit comprises several cascaded stages. The first stage receives the four folded signals and combines them so as to produce four other signals which are again periodic functions of the input analog voltage Vin but, this time, with a period that is double the period of the folded signals: these two signals pass through zero not only when Vin is equal to the reference voltages that have been used for the folding but also for intermediate reference voltages located in the middle of the interval between two adjacent reference voltages. The signals can therefore be used to give an additional information bit with respect to the most significant bits obtained by the coarse converter. The voltages thus obtained at output of the first stage are applied to a second stage which has the same function (the creation of signals with a period that is again doubled) and gives an additional bit for the value of Vin. Continuing in this way, several stages may be cascade-connected to obtain the successive least significant bits of the conversion. It seems that the U.S. Pat. No. 5,126,742 describes an architecture of this type.
Finally, in an architecture recently proposed by the Applicant, there is a combined converter in which the same bridge of resistors is used both as a reference for a coarse converter and for fine interpolation (patent application No. FR 92 14640).
In most architectures of combined converters, it is necessary to see to it that the analog signal to be converted goes first of all into a sample-and-hold circuit. Indeed, the combined converters need a certain period of time to give a complete signal. And the input analog signal should not vary during this period, failing which it is possible that aberrant results might be obtained. For example, in certain architectures, the fine conversion can be done only after a phase of reconstruction of a remainder voltage on the basis of the result of a coarse conversion: the remainder should not vary during reconstruction. Similarly, in the architectures where the fine interpolation is done by series-connected circuits, the input voltage should not vary between the moment of the interpolation in the first stage and the moment of interpolation in the last stages.
A sample-and-hold circuit is therefore planned upline with respect to the converter. It receives an analog voltage Ve to be converted and gives, at its output, a sampled voltage Vin that is the value of Ve measured at the start of a conversion phase. This output voltage Vin is held with high precision throughout the time needed for the conversion, both coarse and fine.
This sampled and held voltage is therefore applied to the coarse converter and is used also by the fine converter.
However, the making of the sample-and-hold circuit is a delicate task. Its dynamic response speed and its precision must be high. It should be capable of sampling and holding an analog signal that varies at high speed with high amplitudes: it should therefore have good characteristics of dynamic linearity. Furthermore, it should be capable of controlling the fairly high input capacitance of the different input circuits of the converter: this capacitance results from the parallel-connection of all the input capacitances of the different amplifiers and comparators, which are sometimes very numerous and which may receive the input voltage Vin in parallel. However, the sample-and-hold circuit should not consume excessive power, the dissipation of power being one of the most important limitations in the making of the precision analog-digital converters.
All these constraints mean that the sample-and-hold circuit is a circuit element that is almost as difficult to make as the analog-digital converter at whose input it is placed.
An aim of the invention is to make the converter less dependent on the limitations of performance introduced by the sample-and-hold circuit.